1. Field of the Invention
The present invention relates generally to a localized direct sense architecture, and more particularly pertains to a localized direct sense architecture which includes a large number (e.g. 8) of microcells, each having a primary sense amp PSA, coupled to one global data line which is coupled to one secondary sense amp SSA. Each PSA includes its own bias current device, which supplies bias current to sense devices in the PSA and is also used for precharge, such that the bias current does not flow along the highly capacitive global data line. With this technical approach, the size of each bias current supply device can be substantially reduced, and the number of PSAs on one global data line can be increased for greater layout density.
2. Discussion of the Prior Art
Direct sense memory arrays are memory arrays wherein only the gate of the sense device/transistor is connected to a sensed bitline BL, such that the sense device does not provide any feedback to or alter the signal on the sensed bitline BL. This is in contrast to other prior art nondirect sense memory arrays which include a cross coupled latch wherein typically both the gate and the drain of a sense device/transistor are connected to a sensed bitline BL, and wherein the sense device provides feedback to and alters the signal on the sensed bitline BL.
Direct sense memory arrays typically use a dense and high speed primary sense amp (PSA) which does not latch sensed data during a read operation, and the sensed data is typically directed to an external cache, from which it is written back into the memory array during a refresh operation, which is a very time consuming operation and also requires the use of the external cache which could otherwise be performing other functions in the system. As such, an accessed memory storage cell does not get directly written back, or restored, after a read operation, but rather has an indirect writeback or restore operation. The basic direct sense read operation is described in U.S. Pat. No. 6,552,944 and entitled Single Bitline Direct Sensing Architecture.
Prior art stabilized direct sense circuits typically mix a bias current generated by a bias current device in a secondary sense amp (SSA) with a signal current along a global data line (PDL). The bias current device is located within the secondary sense amp SSA which is shared by a plurality of n primary sense amps (PSAs) coupled along the global data line PDL, such that the bias current must flow along the highly capacitive global data line PDL.
In the prior art, an array of typically 4 primary sense amps PSAs are connected to one secondary sense amp SSA along a global data line PDL. FIG. 1 illustrates a typical prior art direct sense circuit wherein 4 microcells, each having an associated primary sense amp PSA, are coupled to one global data line PDL, which is coupled to one secondary sense amp SSA having a relatively large bias current supply and a relatively large inverting latch.
Each primary sense amp PSA is relatively simple and typically comprises only:
(1) a pair of NFET devices for sensing and enable;
(2) a pair of write devices;
(3) a pair of bitline restore devices.
The secondary sense amp SSA typically comprises, as illustrated in FIG. 1: 1) a bias current supply device T1 to bias the PSA at its reference level;
(2) a switch T2 to disable the bias current;
(3) an amplifying Inverting Latch, which is typically a cross coupled latch with an internal isolation device;
(4) an output NFET device T3;
(5) a precharge device T4;
(6) a write device T5;
(7) a restore device T6 with 2 buffers.
In the prior art circuit of FIG. 1, the size of the current supply devices T1, T2 must be balanced to the size of the sense devices (which are analogous to the sense devices T9, T12 in the PSA of FIG. 3) to correctly bias the PDL node (analogous to node S in FIG. 3) between data 0 and data 1 responses, which is accomplished with relatively large size devices. However, a problem with this prior art approach is that the relatively large capacitance of the common global data line requires the use of a relatively large size sense device to achieve a high speed operation (which means that the sizes of all of the current supply and switch devices must be increased in proportion) and limits the number of PSAs that can be placed on and coupled to the common global data line.
Accordingly, it is a primary object of the present invention to provide a localized direct sense architecture which places a bias current supply device in each primary direct sense amplifier PSA, such that the bias current does not flow through the global data line PDL, and removes a bias current supply device from the secondary sense amp SSA, where it is normally placed in the prior art. Thus, the bias current is used locally in an active PSA and does not flow along the global data line PDL, which only switches data related current.
The present invention relates to a localized direct sense architecture which includes a large number of microcells, each having a primary sense amp PSA, coupled to one global data line which is coupled to one secondary sense amp SSA. Each PSA includes its own bias current device, which supplies bias current to sense devices in the PSA and is also used for precharge, such that the bias current does not flow along the highly capacitive global data line. With this technical approach, the size of each bias current supply device can be substantially reduced, and the number of PSAs on one global data line can be increased for greater layout density.
The localized direct sense architecture of the present invention results in a smaller sensing system, smaller current supply devices, and faster PDL performance. The size of the direct sense devices and their enable devices can be reduced because the capacitance to which they are coupled is limited to the capacitance within the primary sense amp PSA and does not include the capacitance of a global data line. Hence, one advantageous feature of the present invention is that a higher speed, higher bandwidth design can be achieved with lower currents and with smaller devices than in prior art circuits. Moreover, the size of the secondary sense amp SSA is reduced, and the SSA can be shared by a greater number of microcells than in the prior art.
A refresh/writeback operation occurs at the primary direct sense amp PSA, enabling faster cacheless designs than in the prior art. The writeback/restore operation is moved to the primary sense amp PSA, and is faster to write a data value back into a memory cell because the global data line PDL does not have to be sensed and inverted (complemented) to provide a proper writeback memory cell voltage, as in the prior art wherein the SSA is utilized in the writeback operation.
Additionally, a localized direct sense architecture provides a truly digital output from each PSA onto the global data line PDL, not a small voltage swing analog signal, such that the localized direct sense architecture is more readily tiled or configured into an array of duplicated identical circuits such as in an eDRAM.
Also the localized direct sense LDS architecture allows 100% bitline shielding because only every other bitline is active during a read operation, and the unselected bitlines act as shields to prevent crosstalk which prevents a loss of bitline read signal and also allows a faster cycle.